Cypress Semiconductor /psoc63 /TCPWM0 /CNT[16] /TR_CTRL2

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Interpret as TR_CTRL2

UNDERFLOW_MODE=SET, OVERFLOW_MODE=SET, CC_MATCH_MODE=SET

Description

Counter trigger control register 2

Fields

CC_MATCH_MODE	Determines the effect of a compare match event (COUNTER equals CC register) on the ‘line_out’ output signals. Note that INVERT is especially useful for center aligned pulse width modulation. To generate a duty cycle of 0 percent, the counter CC register should be set to ‘0’. For a 100 percent duty cycle, the counter CC register should be set to larger than the counter PERIOD register. 0 (SET): Set to ‘1’ 1 (CLEAR): Set to ‘0’ 2 (INVERT): Invert 3 (NO_CHANGE): No Change
OVERFLOW_MODE	Determines the effect of a counter overflow event (COUNTER reaches PERIOD) on the ‘line_out’ output signals. 0 (SET): Set to ‘1’ 1 (CLEAR): Set to ‘0’ 2 (INVERT): Invert 3 (NO_CHANGE): No Change
UNDERFLOW_MODE	Determines the effect of a counter underflow event (COUNTER reaches ‘0’) on the ‘line_out’ output signals. 0 (SET): Set to ‘1’ 1 (CLEAR): Set to ‘0’ 2 (INVERT): Invert 3 (NO_CHANGE): No Change

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